In a chip of a semiconductor device (hereinafter referred to as an LSI), various clocks for operating respective circuits is supplied and distributed. However, because of physical variation in manufacturing of elements and wirings in the chip, there is shifts of propagation time, i.e., delay or advance (so called “clock skew”) of each clock, and the clock skew occurs during the each clock reaches the respective circuits. In particular, in an LSI having a strict specification of timing of a clock such as a high operating frequency, it is necessary to adjust a clock skew for each chip after the manufacturing of the LSI. For this purpose, the LSI needs to have a clock skew adjusting circuit in order to supply adjusted clock to respective circuits.
In a scan test for an LSI based on the JTAG (Joint Test Action Group) standard of IEEE1149.1, there is known a method of performing timing adjustment for a clock signal in a delay setting circuit, which uses a delay value stored in a register belonging to a scan chain in which scan setting is possible.
In the scan test for the LSI, there is known a method of adjusting delay in a flip-flop circuit based on a delay value set in a memory in which scan setting is possible.
Further, there is known a clock adjusting device which can adjust, in an LSI including the clock adjusting device, a clock skew which differs in each LSI because of individual product variation and the like of the LSIs.
Furthermore, there is known a semiconductor device which can suppress an increase in a device size for a clock skew adjustment, and can prevent malfunction due to the clock skew, reduction in transfer efficiency due to the clock skew adjustment, and the like.
Patent Document 1: Japanese Laid-Open Patent Publication No. 2001-43261.
Patent Document 2: Japanese Laid-Open Patent Publication No. 2006-332897.
Patent Document 3: Japanese Laid-Open Patent Publication No. 2004-228504.
Patent Document 4: Japanese Laid-Open Patent Publication No. 2005-10958.